1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the fabrication of a capacitor and also to the simultaneous fabrication of capacitors and other devices, such as resistors and also to the simultaneous fabrication of MIM (Metal—Insulator—Metal) capacitors and other devices, such as resistors and capacitors.
2) Description of the Prior Art
It is well known that capacitors are critical components in today's integrated circuits. For example, capacitors play an important role in devices having analog circuits constructed on the integrated circuit chips, often being placed adjacent the device circuitry to carry out de-coupling functions. However, achieving the desired capacitance characteristics is often difficult due to several trends in the industry, namely increasing device density and increasing frequency of operating signals. First, since increased device densities has been achieved largely by the miniaturization of individual devices, it requires a similar miniaturization in capacitor structure, thereby placing a much greater importance on a high capacitance value per unit area. Second, higher operating frequencies have also increased the level of parasitic capacitance and cross-talk experienced between adjacent signal lines or metallization levels thereby increasing the demand upon many capacitors. However, fabrication of capacitance devices within or immediately adjacent the integrated circuit is often limited by design patterning rules. This is particularly true for capacitors intended for use in analog circuitry placed in immediate proximity to the metallization levels.
In addition, current designs can include capacitors and resistors, particularly in RF applications. There is a challenge to develop a manufacturable and cost effect process that can make various capacitors and resistors.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 6,387,770b2(Roy) that reveals a process for forming a MIM Capacitor in a damascene process.
U.S. Pat. No. 6,387,775b1(Jang et al.) shows a method for a MIM Capacitor in a Cu damascene process.
U.S. Pat. No. 6,008,083(Brabazon et al.) teaches a method for a MIM capacitor using two metal layers.
U.S. Pat. No. 6,410,386b12(Hsue et al.) shows a method of a metal capacitor in a damascene process.
U.S. Pat. No. 6,040,596(Choi et al.) discloses a process for a capacitor and a resistor made of the same material as the plate electrode.